(1) Field of the Invention
The present invention relates to a method of fabricating kink-effect-free shallow trench isolations.
(2) Description of the Related Art
In recent years, the distance of the individual transistor had continuously decreased so that the integrated circuit density on chips formed from semiconductor has dramatically increased. In the LOCOS approach, the oxide is selectively grown over the field regions of the ICs. This is done by covering the active regions with a thin layer of silicon nitride. When the field oxide is grown, the active regions remain covered by nitride, which prevents oxidation of the silicon beneath. The oxide grows on the silicon substrate surface where there is no masking nitride. However, at the edges of the nitride, some oxidant diffuses laterally to cause the oxide to grow under and lift the nitride edges that is so called bird's beak effect. The bird's beak will cause serious isolation problems for subsequent processes in the active regions, especially for the submicron and the deep submicron technology. In addition, an implant is performed in the field regions to create a channel-stop doping layer under the field oxide. During field oxidation, the channel-stop boron experiences both segregation and oxidation-enhanced diffusion. Therefore, relatively high boron doses are needed in order for acceptable field threshold voltages to be achieved. This also implies that the peak of the boron implant must be deep enough that it is not absorbed by the growing field-oxide interface. If the channel-stop doping is too heavy, it will cause a high source/drain-to-substrate capacitance and reduce source/drain-to-substrate pn junction breakdown voltage. In order for the application of submicron and deep submicron processes, a new isolation method is desired to replace current LOCOS.
The most probable successor to LOCOS in CMOS is the shallow trench isolation. A typical structure would be formed in the following manner: referring now more particularly to FIGS. 1A, an oxide layer 13 and a nitride layer 15 are sequentially formed on a silicon substrate 11 surface. The oxide layer 13 and a nitride layer 15 are then patterned by the conventional photolithography and the plasma etching technique defines the shallow trench regions 12, which vary significantly in widths at different locations across the surface of the substrate and separate active regions. As a result the surface of the dielectric layer scratches easily when etching the rigid nitride layer 15 and the dielectric layer 17 at the same time by using chemical mechanical polishing (CMP). The scratches form recesses 19, when the active areas 14 and shallow trenches 12 are removed isotropic etching as shown in FIGS. 1B. Furthermore, more serious Oxide-Recesses 19a are formed by the oxidation and etching of the recesses 19 at the sidewall of shallow trenches 12 as shown the dash lines in FIGS. 1B.